Fail-safe signal transmitting apparatus producing a logical product of an input signal and a carrier signal

ABSTRACT

A fail-safe signal transmitting apparatus including a power supply which does not let a transmission output signal generate an error that would allow a dangerous situation to arise even when a multiple failure has occurred in circuits constituting the signal transmitting apparatus. In particular, the present invention includes a source failure monitoring function and in order to monitor the power supply, a fail-safe window comparator and a fail-safe ON delay circuit are employed. An output signal constituted of the logical product of source monitoring signal and a signal to be transmitted and a carrier signal is used as a transmission signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a fail-safe signal transmittingapparatus and a constant voltage power supply. More specifically, thepresent invention relates to a fail-safe signal transmitting apparatuswhich ensures that no error is generated in the output transmissionsignal which would allow a dangerous situation to arise, even when amultiple failure has occurred in circuits that include the power supplyand that constitute a signal transmitting apparatus.

2. Discussion of the Background

In areas such as railway technology, press control, aircraft controltechnology and nuclear power technology which require a high degree ofsafety, a completely fail-safe signal transmitting apparatus, whichoperates in support of its safety function without error in the case ofa circuit failure is absolutely necessary. Fail-safe signal processingtechnology is disclosed in publications such as, U.S. Pat. No.4,661,880, U.S. Pat. No. 5,027,114, U.S. Pat. No. 5,345,138, JapaneseExamined Patent Publication No. 23006/1989 and Japanese Examined PatentPublication No. 2948/1993. By adopting the technology disclosed in thesepublications of prior art, signal transmission can be fail-safe underlimited conditions. However, these publications of prior art do notdisclose a means for securing fail-safe transmission in case of acircuit failure in the signal transmitting apparatus accompanied by afailure in a constant voltage power supply that delivers power to thesignal transmitting apparatus.

Normally, a commercially available constant voltage power supply isprovided with an excess current detector and a protection circuit thatshuts down the output current if an excess current should be supplied tothe load. Such a constant voltage power supply is provided with aconstant voltage circuit which may be a so-called series regulator.However, in a constant voltage power supply provided with an excesscurrent protection circuit, there is no provision for a failure modethat will disable the function for cutting off excess current when thereis a failure in the excess current detection circuit. A fail-safe sourcemonitoring apparatus, which cuts off the output current from theconstant voltage power supply or the output from the processingapparatus that uses the output of the source voltage when a failureoccurs in the excess current protecting apparatus, does not exist in theprior art. In addition, a fail-safe source monitoring apparatus thatcuts off the output if there is a failure in the constant voltage powersupply does not exist in the prior art.

This means that even when the signal transmitting apparatus itself has afail-safe circuit structure, the fail-safe aspect of the entire signaltransmitting apparatus including the power supply is lost in case of acircuit failure in the power supply.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a fail-safe signaltransmitting apparatus that can only generate a transmission outputsignal when the power supply is operating normally and, as a result, isfail-safe against failures in the power supply.

It is a further object of the present invention to provide a signaltransmitting apparatus provided with a fail-safe source monitoringfunction to cut off the output when a failure occurs in the powersupply.

In order to achieve the objects described above, the fail-safe signaltransmitting apparatus according to the present invention uses atransmission signal and a source monitoring signal as input signals andtransmits output signals that correspond to the transmission signalsmentioned above. The fail-safe signal transmitting apparatus accordingto the present invention transmits an output signal constituted of thelogical product of two signals, one being a signal that indicates thatthe transmission signal and the source monitoring signal are normal, andanother being a carrier signal which is used for carrying thetransmission signal. The output signal is not generated when there is afailure.

When there is no circuit failure in the signal transmitting apparatusand a signal indicating that the transmission signal and the sourcemonitoring signal are normal is input, the logical product of thissignal and the carrier signal for carrying the transmission signal istaken and the transmission signal is carried by the carrier signal.

When there is no failure in the signal transmitting apparatus, but acircuit failure has occurred in the power supply, the signal to indicatethat the source monitoring signal is normal is not generated. As aresult, the logical product for carrying the transmission signal is notestablished and the output signal is not generated. Also, in the signaltransmitting apparatus, an output signal is not generated at the time ofa failure. In summary, the signal transmitting apparatus according tothe present invention can generate an output signal on the transmissionside only when the power supply is operating normally.

Preferably, the signal transmitting apparatus according to the presentinvention should include a logical product computing circuit and aswitch circuit. The logical product computing circuit performs logicalproduct calculation of the source monitoring signal and the transmissionsignal and does not generate an output signal when there is a failure.The switch circuit uses the output signal from the logical productcomputing circuit as its source input and is switched with the carriersignal to generate an output signal for the aforementioned transmission.

The signal transmitting apparatus structured as described above does nottransmit erroneous output signals even when there is a multiple failure,such as a shorting failure between the output terminals of the switchcircuit and a failure in the power supply.

It is even more desirable to include a constant voltage circuit and asource monitoring circuit in the signal transmitting apparatus accordingto the present invention. The constant voltage circuit is provided witha series regulator, which is supplied with a voltage created byrectifying and smoothing an AC source, which generates a stabilized DCoutput voltage. The source monitoring circuit includes a level detectingcircuit and an ON delay circuit. The level detecting circuit uses thevoltage being output from the series regulator as its source and alsouses the voltage being input into the series regulator as its monitoringinput. It does not output a signal when there is a failure. The ON delaycircuit uses the signal being output from the level detecting circuit asits input signal and outputs a signal that becomes the source monitoringsignal with a delay relative to the rise of the voltage being outputfrom the level detecting circuit. It does not output a signal at thetime of a failure.

The level detecting circuit and the logical product computing circuitare constituted with fail-safe window comparators.

BRIEF DESCRIPTION OF THE DRAWINGS

The following is a more detailed explanation of other advantages andfeatures of the present invention in reference to the attached drawings.

FIG. 1 is a block diagram showing an example of a signal transmittingapparatus in the prior art and is provided to facilitate betterunderstanding of the present invention;

FIG. 2 is a block diagram showing another example of a signaltransmitting apparatus in the prior art and is provided to facilitatebetter understanding of the present invention;

FIG. 3 is a block diagram of the signal transmitting apparatus accordingto the present invention;

FIG. 4 is a specific circuit diagram of the fail-safe window comparatorused in the signal transmitting apparatus shown in FIG. 3;

FIG. 5 is a block diagram showing the structure of the fail-safe ONdelay circuit employed in the signal transmitting apparatus shown inFIG. 3;

FIG. 6 is a time chart provided to illustrate the operation of thesignal transmitting apparatus shown in FIG. 7;

FIG. 7 is a block diagram of a further specific example of the signaltransmitting apparatus according to the present invention; and

FIG. 8 is a circuit diagram of another embodiment of the signaltransmitting apparatus according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In order to facilitate better understanding of the present invention, asignal transmitting apparatus in the prior art is explained beforeexplaining the present invention. FIG. 1 is a circuit diagram of asignal transmitting apparatus in the prior art. The signal transmittingapparatus shown in FIG. 1 is provided with a power supply 1 and atransmitting circuit 2.

The power supply 1 is provided with a source transformer T0 and diodesD1, D2, D3 and D4 which constitute a full-wave rectifying circuit, asmoothing capacitor C0 and a constant voltage circuit SR, which isnormally constituted with a series regulator. The constant voltagecircuit SR has a function to generate the output of the smoothingcapacitor C0 as a constant source voltage Vcc for the transmittingcircuit 2. A transistor is Q0, located inside the constant voltagecircuit SR performs control between the input and the output of theconstant voltage circuit SR. In a power supply such as described above,there are potential situations in which the output voltage of thesmoothing capacitor C0 is generated directly as the source voltage Vccdue to a shorting failure between the collector and the emitter of thetransistor Q0, or a pulsating current is output as the source voltageVcc because of a disconnection failure in the lead line of the smoothingcapacitor C0.

The transmitting circuit 2 includes a transformer T2 and a transistorQ1. The secondary coil of the transformer T2 is connected with theprimary coil of the transformer T3, which constitutes a receivingcircuit, with lines b1 and c1. The transistor Q1 is switched by analternating signal P1, which is included in an input signal I1indicating safety, and is not switched by a signal P0 indicating danger.Since the collector of the transistor Q1 is connected to the primarycoil of the transformer T2, when the signal P1 of the input signal I1 isbeing input to the transistor Q1, this alternating signal is output atthe secondary coil of the transformer T2. When the signal P1 of theinput signal I1 is not input, i.e., when the signal P0 is being input,no alternating signal is generated in the output of the secondary coilof the transformer T2. The signal being output from the transformer T2is supplied to the primary coil of the transformer T3 and thealternating signals P1, P0, which correspond to the input signal I1 areregenerated as a signal OU1 at the secondary coil of the transformer T3.

Now, the characteristics of the signal transmitting apparatus shown inFIG. 1 at the time of a failure are examined. When there is a failure inthe transistor Q1, i.e., when there is a shorting failure between thecollector and the emitter of the transistor Q1, when there is adisconnection failure at the collector terminal, or when there is adisconnection failure at the primary coil or the secondary coil ofeither one of the transformers T2 and T3, the input signal I1 is notregenerated as the signal OU1 from the transformer T3. In this aspect,the apparatus shown in FIG. 1 is fail-safe. However, if after there hasbeen a shorting failure between the collector and the emitter of thetransistor Q1, there is also a disconnection failure in the smoothingcapacitor C0 of the power supply that generates the source voltage Vccand noise enters via the source transformer T0, the noise is applied tothe transformer T2 via the series regulator. Such noise includes noisewith great amplitude that is generated in an external invertor source,for instance. This noise will be communicated to the transformer T2 andis generated as an erroneous alternating signal output OU1. Thus, theapparatus shown in FIG. 1 has a problem in that, if there is a shortingfailure in the transistor Q1 and there is also a failure in the powersupply that supplies the source power to the transmitting circuit, it isdirectly exposed to the noise entering from the source.

FIG. 2 is a circuit diagram of another signal transmitting apparatus inthe prior art. This apparatus is provided with an optically coupledelement P11 as a means for transmitting signals to the transfer lines b2and c2. The input signal I1 to be transmitted is constituted with thesignals P1 and P0 as in the case of the prior art apparatus shown inFIG. 1. The signal PI is applied to the base of the transistor Q1 in thesame manner as in the prior art apparatus shown in FIG. 1 and with this,a light emitting element PT1 of the optically coupled element PI1 isswitched. A resistor R1 is a current decreasing resistor and Vcc is thesource voltage supplied from the power supply 1. The signal that isswitched at the transistor Q1 is communicated to a light receivingelement PD1 via the optically coupled element PI1. The source on thereceiving side is applied to this light receiving element PD1 via thecurrent decreasing resistor (not shown) and the light emitting elementon the receiving side. When the light receiving element PD1 on thetransmitting side is switched by the light emitting element PT1, thecurrent that runs through the light emitting element on the lightreceiving side (not shown) is switched.

Next, the operation of the signal transmitting apparatus shown in FIG. 2at the time of a failure is explained. The failure modes include, forinstance, a shorting failure between the collector and the emitter ofthe transistor Q1, a disconnection failure of the collector of thetransistor Q1, a disconnection failure of the resistor R1 and adisconnection failure of the light emitting element PT1 or the lightreceiving element PD1. When one of these failures has occurred, a switchsignal is not generated from the light receiving element PD1. Also, whenthere is a shorting failure in the light emitting element PT1, the lightemitting element PT1 does not emit light and therefore, the lightreceiving element PD1 is not switched. When there is a shorting failurein the light receiving element PD1, too, the light receiving element PD1does not undergo the switching operation. Thus, the signal transmittingapparatus shown in FIG. 2 is fail-safe in this aspect.

However, if a disconnection failure occurs in the smoothing capacitor C0of the power supply 1 in a state in which a shorting failure hasoccurred between the collector and the emitter of the transistor Q1,noise entering from the source transformer T0 is applied to the lightemitting element PT1. Thus, with the signal transmitting apparatus inFIG. 2, there is the danger of an erroneous output signal beinggenerated when failures have occurred in the apparatus itself as well asin the power supply 1.

Reflecting the problems of the prior art described above, the presentinvention, by monitoring for failures in the power supply, ensures thatthe transmission-side output signal may be generated only when the powersupply is operating normally.

FIG. 3 is a block diagram showing the structure of the signaltransmitting apparatus according to the present invention. The signaltransmitting apparatus in the figure includes a power supply 11, asource monitoring circuit 12 and a transmitting circuit 13. Referencenumber 14 indicates a signal generating source that generates signals tobe transmitted.

The AC source (commercial source) which is stepped down by a sourcetransformer Trs included in the power supply 11 is then rectified in afull-wave rectifying circuit constituted of the diodes Ds1 to Ds4 andthen smoothed in a smoothing capacitor Cs1. The rectified voltage Vrec,which has been smoothed, is converted into a constant source voltage Vccfor the transmitting signal at a constant voltage circuit SR. FIG. 3shows the simplest example of the constant voltage circuit SR, in whichan electrical current is supplied to a constant voltage diode ZD via acurrent decreasing resistor R0 from the collector of a transistor Qs andthe voltage between the terminals of the constant voltage diode ZD isapplied between the base and the emitter of the transistor Qs. Such aseries regulator is the most commonly known type.

The source monitoring circuit 12 is provided with a fail-safe leveldetecting circuit 15 and a fail-safe ON delay circuit 16. The fail-safelevel detecting circuit 15 uses the source voltage Vcc being output fromthe constant voltage circuit SR as a source potential to perform leveldetecting of the DC voltage Vrec being input into the constant voltagecircuit SR. In the present invention, the fail-safe level detectingcircuit 15 is constituted with a fail-safe window comparator. Such awindow comparator is already known, disclosed in U.S. Pat. No. 4,661,880and U.S. Pat. No. 5,027,114.

FIG. 4 shows an example of a window comparator described above. Thewindow comparator in the figure is provided with a feedback oscillatingcircuit 150. The feedback oscillating circuit 150, in turn, includes aDC amplifying circuit 151 and a DC amplifying circuit 152. The DCamplifying circuit 151 comprises transistors Q31, Q32 and Q33 and the DCamplifying circuit 152 comprises transistors Q35, Q36 and Q38. Atransistor Q34 and a resistor R39, which constitute an invertor, areconnected between the DC amplifying circuit 151 and the DC amplifyingcircuit 152. The DC amplifying circuit 151 and the DC amplifying circuit152 are linked via the invertor which is constituted with the transistorQ34 and the resistor R39, resistors R38 and R40 and a feedback resistorRf to constitute a feedback oscillating circuit 150. With the sourcevoltage at Vcc and the input voltages at the input terminals T1 and T2referred to as V1 and V2 respectively, this feedback oscillating circuit150 oscillates when the input voltages V1 and V2 at the input terminalsT1 and T2 satisfy the following conditions:

    (R31+R32+R33)Vcc/R33<V1<(R36+R37)Vcc/R37                   (1),

    (R41+R42+R43)Vcc/R43<V2<(R46+R47)Vcc/R47                   (2).

The feedback oscillating circuit 150 described above oscillates onlywhen the input voltage V1 at the input terminal T1 and the input voltageV2 at the input terminal T2 satisfy the conditions (1) and (2) aboverespectively.

In addition, since oscillation cannot be performed if there is a failurein any one of the transistors Q31 to Q41 that constitute the feedbackoscillating circuit 150, or if there is a disconnection failure in aresistor, it fulfills a function as a fail-safe AND gate.

In addition, in the following conditions which are obtained based uponconditions (1) and (2),

    (R31+R32+R33)Vcc/R33≈V1                            (3),

    (R41+R42+R43)Vcc/R43≈V2                            (4);

the input voltage V1 in condition (3) indicates the lower limitthreshold value that should be applied to the input terminal T1 in orderfor the feedback oscillating circuit 150 to oscillate. Hereafter, thelower limit threshold value of the input voltage V1 that must be appliedto the input terminal T1 will be indicated as TL1. Likewise, the inputvoltage V2 in condition (4) represents the lower limit threshold valuethat must be applied to the input terminal T2 in order for the feedbackoscillating circuit 150 to oscillate. Hereafter, the lower limitthreshold value that must be applied to the input terminal T2 will beindicated as TL2.

Next, in the following conditions which are obtained based uponconditions (1) and (2),

    (R36+R37)Vcc/R37≈V1                                (5),

    (R46+R47)Vcc/R47≈V2                                (6);

the input voltage V1 in condition (5) indicates the upper limitthreshold value that must be applied to the input terminal T1 in orderfor the feedback oscillating circuit 150 to oscillate. Hereafter, theupper limit threshold value of the input voltage V1 that must be appliedto the input terminal T1 will be indicated as TH1. Likewise, the inputvoltage V2 in condition (6) represents the upper limit threshold valuethat must be applied to the input terminal T2 in order for the feedbackoscillating circuit 150 to oscillate. Hereafter, the upper limitthreshold value that must be applied to the input terminal T2 will beindicated as TH2. Note that the threshold values TL1, TL2, TH1, TH2described above are potentials that are higher than the source potentialVcc (TL1, TL2, TH1 and TH2>Vcc).

The window comparator shown in FIG. 4 further includes an amplifyingcircuit 153 and a voltage doubler rectifying circuit 154. The amplifyingcircuit 152 amplifies the signal being output from the transistor Q38which is included in the feedback oscillating circuit 150. Theamplifying circuit 153 in the figure includes diodes D31 and D32,resistors R48, R49 and R50 and transistors Q39, Q40 and Q41 and performsON/OFF operation with the oscillation of the transistors Q39, Q40 andQ41. The voltage doubler rectifying circuit 154 includes capacitors C31and C32 and diodes D33 and D34.

When the feedback oscillating circuit 150 oscillates, the transistor Q38is switched. During this switching operation, when the transistor Q38enters the ON state, the transistor Q39 shifts to the OFF state and,with this, the input potential of the voltage doubler rectifying circuit154 becomes approximately equal to the source potential. When thetransistor Q38 enters the OFF state, the transistor Q39 shifts to the ONstate and, with this, the input potential of the voltage doublerrectifying circuit 154 becomes a ground potential (0 level). Thecapacitor C31 and the diode D33 cause the change in the input potentialof the voltage doubler rectifying circuit 154 to be clamped by thesource potential Vcc and rectified and smoothed by the diode D34 and thecapacitor C32. The capacitor C32 is shown as a 4-terminal capacitor.This 4-terminal capacitor is a capacitor of the prior art that is oftenused because of its structure, which does not allow the generation ofoutput signals when a disconnection failure occurs in a lead line. If aregular capacitor other than a 4-terminal capacitor is used for thecapacitor C32, the signal being output from the diode D34 (in otherwords, the switch signal of the amplifier 153) is clamped by the sourcepotential Vcc and is output when a disconnection failure has occurred ina lead line of the capacitor. However, even when this happens, the ACsignal output from the diode D34 is not erroneously generated unless thetwo input signals of the feedback oscillating circuit 150 satisfy therequirements expressed in conditions (1) and (2). In particular, if theoutput signal from the window comparator is input to the fail-safe ONdelay circuit 16, to be explained later, as shown in FIG. 3, thecapacitor does not necessarily have to be a 4-terminal capacitor.

Referring back to FIG. 3, the level detecting circuit 15, which isconstituted with a fail-safe window comparator, performs level detectingfor the rectified voltage Vrec to the constant voltage circuit SR whichis included in the power supply 11. The level detecting circuit 15generates a level detecting output signal y1 if the rectified voltageVrec is higher than a specific level (assuming that the upper limitthreshold values TH1 and TH2 are high enough). In an embodiment in whichthe level detecting circuit 15 is constituted with a fail-safe windowcomparator, if the rectified voltage Vrec is higher than the lower limitthreshold values TL1 and TL2 of the fail-safe window comparator, thefail-safe window comparator oscillates and then a rectified outputvoltage (E) is generated from the voltage doubler rectifying circuit 154(see FIG. 4). In the case of the embodiment shown in FIG. 3, the lowerlimit threshold value TL1 at the input terminal T1 and the lower limitthreshold value TL2 at the input terminal T2 are equal to each other andthe input terminal T1 and the input terminal T2 (see FIG. 4) of thefail-safe window comparator are connected commonly, to function as asingle input terminal.

The fail-safe ON delay circuit 16 is a delay circuit in which a sourcemonitoring signal y2 rises with a specific delay period after the riseof the level detecting signal y1 output from the level detecting circuit15, which is constituted with a fail-safe window comparator. Fail-safeON delay circuits are disclosed in Japanese Examined Patent PublicationNo. 23006/1989 and U.S. Pat. No. 5,027,114. The fail-safe ON delaycircuit disclosed in Japanese Examined Patent Publication No. 23006/1989employs a UJT (unijunction transistor) oscillating circuit while U.S.Pat. No. 5,027,114 discloses an ON delay circuit that employs a CRcircuit.

FIG. 5 shows an example of a fail-safe ON delay circuit that employs aPUT (programmable unijunction transistor) oscillating circuit. Thisfail-safe ON delay circuit is, in principle, identical to the onedisclosed in Japanese Examined Patent Publication No. 23006/1989described above. The fail-safe ON delay circuit shown in FIG. 5 isprovided with a PUT oscillating circuit 161, a fail-safe windowcomparator 162 and rectifying circuits 163 and 164.

The PUT oscillating circuit 161 is an oscillating circuit in the knownart in which, when a signal (E) whose potential is higher than thesource potential Vcc is input as a signal y1, a pulse PU is output aftera specific length of time, which is determined by the ratio of dividedvoltages of the resistors Ra and Rb, and the time constant of theresistor RT and the capacitor CT has elapsed.

The window comparator 162 is identical to the one shown in FIG. 3. Sincethe signal y1 is also input to the input terminal T2 of the windowcomparator, when a signal y1, which is higher than the lower limitthreshold value TL2 at the input terminal T2, is input, the output pulsePU, which corresponds to the delay time in the PUT oscillating circuit161, is input to the input terminal T1 of the window comparator from thePUT oscillating circuit 161. This output pulse PU is at a higher levelthan the lower limit threshold value TL1 at the input terminal T1 of thewindow comparator 162. Thus, the window comparator 162 oscillates. Sincethe signal being output from the rectifying circuit 164 that resultsfrom this oscillation is fed back to the input terminal T1 via aresistor Rf1, a self-holding operation is performed, whereby the inputvoltage is continuously applied to the input terminal T1 even when theoutput pulse PU of the PUT oscillating circuit 161 becomes extinct.Then, only when the signal y1 becomes lower than the lower limitthreshold value at the input terminal T2, does the source monitoringsignal y2 become extinct. The PUT oscillating circuit 161 shown in FIG.5 has a characteristic such that, if there is a disconnection failure inany of the resistors Ra, Rb and RT, which constitute the circuit, adisconnection or shorting failure occurs in the capacitor CT or afailure occurs in the PUT, oscillation cannot be performed (the outputpulse PU is not generated). Note that the upper limit threshold values(TH1, TH2) of the window comparator employed to constitute the ON delaycircuit 16 in FIG. 5 are set at sufficiently high levels and thethreshold values of the window comparator are set in such a manner that,if a voltage higher than the lower limit threshold value (TL1, TL2) isinput, oscillation is performed.

The rectifying circuits 163 and 164 are structured almost identically tothe rectifying circuit 154 shown in FIG. 3. The signal being output fromthe rectifying circuit 164 is fed back to the input terminal T1 via thefeedback resistor Rf1 to constitute a self-holding circuit. A holdingcircuit that employs a window comparator in this manner is alsodisclosed in U.S. Pat. No. 5,027,114.

Referring back to FIG. 3. again, the signal transmitting circuit 13 usesthe transmission signal x1 and the source monitoring signal y2 as inputsignals and transmits a signal that corresponds to the transmissionsignal x1. The signal transmitting circuit 13 transmits the logicalproduct signal of the signal indicating that the transmission signal x1and the source monitoring signal y2 are normal and a carrier signal x2for carrying the transmission signal. At the time of a failure, theoutput signal is not generated. To be more specific, the signaltransmitting circuit 13 includes a logical product computing circuit 17and a switch circuit 18. The logical product computing circuit 17performs the logical product calculation to calculate the logicalproduct of the source monitoring signal y2 and the transmission signalx1. The logical product computing circuit 17 is structured as a circuitthat does not output a signal at the time of a failure. Such a logicalproduct computing circuit 17 may be achieved with the fail-safe windowcomparator shown in FIG. 4.

The switch circuit 18 uses the signal being output from the logicalproduct computing circuit 17 as a source, is switched by the carriersignal x2 and generates an output signal for transmission.

Next, in reference to the time chart in FIG. 6, the circuit operation ofthe signal transmitting apparatus shown in FIG. 3 is explained.

The lower limit threshold value TL (TL1=TL2) of the fail-safe windowcomparator that constitutes the level detecting circuit 15 is setbetween the rectified voltage Vrec being output from the full-waverectifying circuit, which is constituted with the diodes Ds1 to Ds4under normal conditions, and the voltage Vcc being output from theseries regulator. As a result, when the voltage Vrec being output fromthe full-wave rectifying circuit is normal, and the constant voltagecircuit SR is operating normally, the fail-safe window comparator, whichconstitutes the level detecting circuit 15, oscillates, which, in turn,generates a rectified output voltage (E) as the output signal y1. (seeFIG. 4) The fail-safe ON delay circuit 16, too, generates a voltagewhich is equal to the rectified output voltage (E), as the sourcemonitoring signal y2 (see FIG. 4).

Now, consider a hypothetical situation in which a disconnection failurehas occurred in a lead line of the smoothing capacitor Cs1, whichconstitutes the power supply 11, and this disconnection failure has beenrestored to normal. Such a failure seldom occurs in reality, but thishypothesis is considered here in order to facilitate the explanation ofthe operation of the signal transmitting apparatus in FIG. 3. FIG. 6,time chart (1) shows the waveform being output from the full-waverectifying circuit in this situation. Next, referring to time chart (1),the period in which a pulsating current, due to the disconnection of thelead line of the smoothing capacitor Cs1, is generated will beconsidered. Time chart (2) shows the waveform of the voltage beingoutput from the constant voltage circuit SR and, when the voltage Vrecbeing input into the constant voltage circuit SR is smaller than thesource voltage potential Vcc, the voltage being output from the constantvoltage circuit SR conforms to the waveform being output from thefull-wave rectifying circuit. The lower limit threshold value TL(TL1=TL2) of the fail-safe window comparator, which constitutes thelevel detecting circuit 15, is set higher than the voltage Vcc beingoutput from the constant voltage circuit SR. Because of this, when thevoltage being input into the constant voltage circuit SR starts todecrease, the voltage being output from the constant voltage circuit SRstill maintains the potential of the constant voltage Vcc, but when thevoltage Vrec becomes lower than the threshold value TL, the fail-safewindow comparator, which constitutes the level detecting circuit 15,will have already stopped oscillating, thus the signal y1 (the rectifiedoutput voltage (E) becoming extinct. Since the signal y1 is clamped bythe source potential Vcc (see FIG. 4), when the voltage being outputfrom the constant voltage circuit SR becomes reduced, the signal y1 alsobecomes reduced in conformance. This operation is shown in time chart(3).

When the fail-safe window comparator that constitutes the leveldetecting circuit 15 stops oscillating, thus setting the signal y1 tolow, the source monitoring signal y2 of the fail-safe ON delay circuit16 is also set to low. Moreover, since the fail-safe window comparatorconstituting the level detecting circuit 15 is set to high only duringthe period of time in which the waveform being output from the full-waverectifying circuit exceeds the threshold value TL, if the rise delaytime (ToN) of the fail-safe ON delay circuit 16 is longer than this timeperiod T, the source monitoring signal y2 generated from the fail-safeON delay circuit 16 does not generate the output voltage (E), the levelof which is higher than the source potential Vcc while there is adisconnection failure in the lead line of the capacitor Cs1. Thus, thesource monitoring signal y2 becomes a signal at the level (E), which ishigher than the source potential Vcc, only when the delay time ToN ofthe fail-safe ON delay circuit 16 has elapsed after recovery from thedisconnection failure in the lead line of the capacitor Cs1, as shown intime chart (4).

Now, in the circuit shown in FIG. 3, when a disconnection failure occursin at least one of the diodes Ds1 to Ds4 constituting the full-waverectifying circuit and the voltage Vrec being input into the constantvoltage circuit SR becomes equal to or less than the threshold value TLby an increase which is equivalent to a ripple, for instance, the sourcemonitoring signal y2 of the fail-safe ON delay circuit 16 does notgenerate an output voltage whose level is higher than that of the sourcepotential Vcc. Also, when there is a shorting failure between the inputand the output of the constant voltage circuit SR (shorting between thecollector and the emitter of the transistor Qs in FIG. 3), too, avoltage that is equal to the source voltage is input to both the inputterminals T1 and T2 of the fail-safe window comparator constituting thelevel detecting circuit 15 and, as a result, the fail-safe windowcomparator cannot perform oscillation. Consequently, the sourcemonitoring signal y2 does not become an output voltage whose level ishigher than the source potential. In this case, the source potentialbecomes the voltage Vrec being input into the constant voltage circuitSR.

When there is no circuit failure in the signal transmitting circuit 13and a signal which indicates that the transmission signal x1 and thesource monitoring signal y2 are normal is input to the logical productcomputing circuit 17, the logical product of this signal and the carriersignal x2 for carrying the transmission signal x1 is taken into theswitch circuit 18 and the transmission signal x1 is carried by thecarrier signal x2.

In the event that, while there is no failure in the signal transmittingcircuit 13, a circuit failure such as described earlier has occurred inthe power supply 11, no signal indicating that the source monitoringsignal y2 is normal is generated. Consequently, the logical product forcarrying the transmission signal x1 is not established and, thus, anoutput signal z is not generated. Moreover, the output signal z is notgenerated in the signal transmitting circuit 13 at the time of afailure. In summary, the signal transmitting circuit 13 according to thepresent invention can generate the output signal z only when the powersupply 11 is operating normally.

In addition, even when a multiple failure occurs, such as a shortingfailure between the output terminals of the switch circuit 18 togetherwith a failure in the power supply 11, an output signal z is noterroneously transmitted.

FIG. 7 shows a more specific embodiment of the fail-safe signaltransmitting apparatus according to the present invention. In FIG. 7,the logical product computing circuit 17 includes a fail-safe windowcomparator 171 and a rectifying circuit 172. The fail-safe windowcomparator 171 and the rectifying circuit 172 that constitute thelogical product computing circuit 17 may be the same as those shown inFIG. 4. The source monitoring signal y2 of the failure monitoringcircuit of the power supply in the transmitting circuit is input to theinput terminal T1 of the fail-safe window comparator 171 and the signalx1 to be transmitted is input to the input terminal T2. The input signaly2 at the input terminal T1 is a failure monitoring output signal in thepower supply 11 of the transmitting circuit and corresponds to thesource monitoring signal y2 being output from the fail-safe ON delaycircuit 16, in FIG. 3. The input signal x1 at the input terminal T2 is asignal that contains the signal (information) to be transmitted and asignal that is being output from a signal generating source 14constituted with an optical sensor in the example shown in FIG. 7.

The signal generating source 14 includes an optical sensor, forinstance, as a fail-safe sensor. Such a sensor is disclosed in U.S. Pat.No. 5,345,138. The signal generating source 14 is constituted with alight projector 141 and a light receiver 142. An AC light that is outputfrom the light projector 141 as an optical beam PB undergoesoptical/electrical signal conversion and is amplified by the lightreceiving element. It is then rectified in the voltage doublerrectifying circuit, which is constituted with the capacitors C11, C12and the diodes D11, D12 and this then becomes a DC signal.

Since the voltage doubler rectifying circuit is constituted in such amanner that the input signal is clamped by the source potential Vcc,when the AC output signal of the light receiver 142 is generated, anoutput voltage whose potential is higher than the source potential Vccis supplied to the input terminal T2 of the window comparator. Thesignal generating source 14 indicates danger when the optical beam PB isblocked and indicates safety when it is not blocked, while monitoringthe danger area. As a result, it indicates safety when an AC outputsignal is generated at the light receiver 142 and a DC signal of thevoltage doubler rectifying circuit constituted with the capacitors C11and C12 and the diodes D11 and D12 is applied to the input terminal T2,and it indicates danger when a DC signal whose level is higher than thatof the source potential Vcc is not applied to the input terminal T2 in astate in which an AC output signal is not being generated in the lightreceiver 142.

The switch circuit 18 includes a transistor Q12 whose base is driven bya carrier signal generator 19 and an optically coupled element PI11,which is connected to the collector of the transistor Q12. The collectorof the transistor Q12 in the switch circuit 18 is led to the outputterminal of the logical product computing circuit 17 via the opticallycoupled element PI11; a current decreasing resistor R11 and the voltagedoubler rectifying circuit 172, so that the switch circuit 18 operatesusing the output from the logical product computing circuit 17 as itspower source.

The logical product computing circuit 17, which includes a windowcomparator, performs level detecting to determine whether or not theupper limit threshold values TH1 and TH2 are sufficiently high and alsowhether or not voltages whose levels are higher than the sourcepotential Vcc are being input to the input terminals T1 and T2 for thelower limit threshold values TL1 and TL2 respectively. When voltagesthat are higher than the threshold values TL1 and TL2 are input to theinput terminals T1 and T2 respectively, the logical product computingcircuit 17 supplies an output signal for oscillation to the rectifyingcircuit 172 (the logical product computing circuit 17 operates as an ANDgate). The significance of the window comparator 171 operating as an ANDgate is that, provided that the power supply 11 is operating normally,the output signal x1 from the optical sensor is sent to the rectifyingcircuit 172 via the window comparator 171 to generate an output from therectifying circuit 172.

The transistor Q12 is switched by the signal being output from thecarrier signal generator 19, using the rectified voltage of therectifying circuit 172 for the power source. The collector of thetransistor Q12 is connected to the capacitor Q14 via the currentdecreasing resistor R11 and a light emitting element PT12 of theoptically coupled element PI11 so that the voltage being output from thevoltage doubler rectifying circuit 172 is used as a source voltage. Theemitter of the transistor Q12 is connected to the source potential Vccin the transmitting circuit. Thus, the base of the transistor Q12 musthave a higher input level than the source potential Vcc. The signal x2being output from the carrier signal generator 19 is clamped by thesource potential Vcc with the capacitor C15 and the diode D15, and itbecomes a base input signal at the transistor Q12 via a currentdecreasing resistor R13. The resistor R12 is a leak resistor of thetransistor Q12. The electrical current, which is switched by thetransistor Q12, turns ON/OFF the light emission of the light emittingelement PT12 in the optically coupled element PI11 and also turns ON/OFFa light receiving element PD12.

In the structure shown in FIG. 7, the current that runs through thelight emitting element PT12 in the optically coupled element PI11 issupplied from the voltage doubler rectifying circuit 172 and unless arectified output voltage (E) that is higher than the source potentialVcc is generated in the voltage doubler rectifying circuit 172, thelight emitting element PT12 does not emit light. In other words, thelight emitting element PT12 sends an optical switch signal to the lightreceiving element PD12 when both the signal being output from thevoltage doubler rectifying circuit 172 and the signal being output fromthe carrier signal generator 19 are input to the transistor Q12, and thesignal being output from the light emitting element PT12 is generated bythe logical product of the signal being output from the voltage doublerrectifying circuit 172 and the signal x2 being output from the carriersignal generator 19. Even if a shorting failure occurs between thecollector and the base of the transistor Q12 and, in probabilityresulting in a state in which the light emitting element PT12 isdirectly driven by the carrier signal generator 19 via the resistor R13,the light emitting element PT12 does not generate light emission outputbecause the resistance value in the resistor R13 is high. This meansthat the light emitting element PT12 generates an AC light output signalonly when the transistor Q12 is operating normally and a voltage that ishigher than the source potential Vcc is supplied from the voltagedoubler rectifying circuit 172. It goes without saying that when thereis a failure in the light emitting element PT12 or the light receivingelement PD12, too, no AC signal emerges at the output terminals U1 andU2.

In reference to FIG. 7, a voltage whose level is higher than the sourcepotential Vcc is output from the voltage doubler rectifying circuit 172when all of the following conditions are satisfied; (a) when the signaly2, which indicates that the power supply is operating normally, isbeing output from the fail-safe ON delay circuit 16 performing sourcemonitoring, (b) a signal P1, which indicates safety is received from thelight receiver 142 of the optical sensor, (c) this received signal P1 isrectified in the voltage double rectifying circuit constituted with thediodes D11 and D12 and the capacitors C11 and C12, and (d) the rectifiedsignal is input to the input terminal T2 of the fail-safe windowcomparator 171 constituting the logical product computing circuit 17. Inthe above process, the signal x1 at the input terminal T2 of thefail-safe window comparator 171 contains a signal (information) which isthe purpose of transmission of the transmitting circuit shown in FIG. 7.The transmitting circuit shown in FIG. 7, which is constituted with thefail-safe window comparator 171, a current decreasing resistor R11, thelight emitting element PT12 and the switch element Q12 constituted of atransistor, outputs a logical product signal from the light emittingelement PT12 constituted of the logical product of the following threeinput signals: i.e., the monitoring signal y2 from the power supply thatis input to the input terminal T1, the signal x1, which is used as thetransmission signal and is input to the input terminal T2 and thecarrier signal x2, which is input to the base of the transistor Q12. Ifany one of these three signals is not input, or if there is a failure inthe circuit, the output from the light emitting element PT12 is notgenerated in this circuit.

Now, a case is examined in which a failure occurs in the power supply.

In the signal transmitting apparatus shown in FIG. 7, when a failureoccurs in the power supply 11 shown in FIG. 3, the fail-safe ON delaycircuit 16 does not output the signal y2 at a high level voltage (E)during a specific length of delay time ToN, even if the source voltagein the transmitting circuit recovers from a low level state to aspecific constant voltage Vcc. Consequently, since the voltage at theinput terminal T1 of the fail-safe window comparator 171 remains at loweven if the constant voltage Vcc temporarily recovers to a normalvoltage having the waveform shown in time chart (1) in FIG. 6, thefail-safe window comparator 171 does not oscillate. In addition, if ashorting failure occurs between the input and the output of the constantvoltage circuit SR shown in FIG. 3, the constant voltage Vcc at each ofthe blocks constituting the transmitting circuit becomes the voltageVrec being input into the series regulator. In other words, while thesource potential Vcc in FIG. 6 increases to the level of the voltageVrec, the input signal at the input terminal T1 of the fail-safe windowcomparator 171, too, requires an input voltage that is higher than thisnew source potential Vrec, and a voltage higher than this source voltageVrec is required for the source voltage of the transistor Q12 (thevoltage that should be generated in the rectifying circuit 172). Thus,since a level that is higher than that of the source voltage Vrec is notgenerated in the fail-safe ON delay circuit 16 in FIG. 3, no signal isgenerated in the light emitting element PT12.

While FIG. 7 shows an example in which an optically coupled element isused as a means for transmission, it is obvious that the same advantagescan be achieved using a transformer instead of the optically coupledelement.

FIG. 8 shows an example in which an optically coupled element PI22 isemployed to replace the coupling of the base of the transistor Q12 andthe signal x2 being output from the carrier signal generator 19 in FIG.7. In FIG. 8, the signal x2 being output from the carrier signalgenerator 19 is input to a light emitting element PT22 of the opticallycoupled element PI22, the optical output of the light emitting elementPT12 is switched by the signal x1 being output from the carrier signalgenerator 19 by using a transistor Q13, and the electrical currentrunning through the light emitting element PT22 is thereby switched.With this, the light emitting element PT12 of the optically coupledelement PI11 is switched and the transmission output signal isgenerated. With the transmitting circuit shown in FIG. 8, the concernabout the error of the carrier signal x2 being directly output due toshorting between the collector and the base of the transistor Q12 shownin FIG. 7 is totally eliminated.

According to the present invention, a fail-safe signal transmittingapparatus which does not generate an erroneous transmission signal thatcould result in a dangerous situation, even when a multiple failure,including a failure in the source, has occurred and, as a result, isextremely effective in a communication system that is required toprovide a high degree of safety.

We claim:
 1. A fail-safe signal transmitting apparatus comprising:alogical product computing circuit; a switch circuit; a transmissionsignal and a source monitoring signal as input signals; an output signalcorresponding to said transmission signal and constituted of a logicalproduct of a signal indicating that said transmission signal and saidsource monitoring signal are normal and a carrier signal for carryingsaid transmission signal is transmitted and said output signal is nottransmitted at a time when said monitoring signal and said transmissionsignal are not normal; wherein said logical product computing circuitperforms logical product calculation for said source monitoring signaland said transmission signal and does not generate an output signal inthe event that either signal is abnormal; and said switch circuit usingsaid output signal of said logical product computing circuit as a sourceinput, said switch circuit being switched by said carrier signal andgenerating said output signal.
 2. A fail-safe signal transmittingapparatus according to claim 1, wherein;said switch circuit includes anoptically coupled element.
 3. A fail-safe signal transmitting apparatusaccording to claim 1 further comprising:a voltage stabilizing circuitwhich includes a series regulator with an input voltage obtained byrectifying and smoothing an AC source supplied to said series regulatorto generate a stabilized DC output voltage; a source monitoring circuitwhich is provided with a level detecting circuit and an ON delaycircuit; said level detecting circuit does not generate an output signalin the event of a failure, using an output voltage of said seriesregulator as power source and an input voltage of said series regulatoras a monitoring input; and said ON delay circuit is a circuit that usesan output signal of said level detecting circuit as an input signal togenerate an output signal that becomes said source monitoring signalwith a delay relative to the rise of an output voltage from said leveldetecting circuit, while said output signal is not generated in theevent of failure.
 4. A fail-safe signal transmitting apparatus accordingto claim 3, wherein:said switch circuit includes an optically coupledelement.
 5. A fail-safe signal transmitting apparatus according to claim3, wherein;said level detecting circuit and said logical productcomputing circuit each include a fail-safe window comparator.
 6. Afail-safe signal transmitting apparatus according to claim 5,wherein:said switch circuit includes an optically coupled element.
 7. Apower supply provided with a voltage stabilizing circuit and a sourcemonitoring circuit, wherein:said voltage stabilizing circuit includes aseries regulator with a DC input voltage supplied to said seriesregulator to generate a stabilized DC output voltage; said sourcemonitoring circuit is provided with a level detecting circuit and an ONdelay circuit; said level detecting circuit does not generate an outputsignal in the event of a failure, using an output voltage of said seriesregulator as a power source and an input voltage of said seriesregulator as a monitoring input; and said ON delay circuit is a circuitthat uses an output signal of said level detecting circuit as an inputsignal to generate an output signal with a delay relative to the rise ofan output voltage of said level detecting circuit, while said outputsignal is not generated in the event of a failure.
 8. A power supplyaccording to claim 7, wherein;said level detecting circuit isconstituted of a fail-safe window comparator and a carrier signal isused as a transmission signal.